1. Field of the Invention
The present invention relates to decoding of Digital Video Cassette video images and more particularly to decoding variable length coded data to provide a data stream of decoded data.
2. Description of the Related Arts
As computers become more and more powerful, the fascination of consumers and professionals alike with digital graphics becomes more and more acute. Digital graphics enable users to manipulate, transfer and store the digital graphics as data files on computers. Digital cameras are one of the first devices to take advantage of digital capture without demanding an intermediate step of first scanning the particular graphic depiction. On the heels since the introduction of the digital cameras are digital video recorders. Albeit the current prices for digital video recorders are not for the average consumer or even professional, there is still an outpouring of next generation digital video camcorders that are available. However, as the digital video camcorders become more widely accepted, the prices of the digital camcorders will drop allowing many consumers to afford the digital camcorders.
One inherent impasse of the digital video camcorders or even digital cameras is converting and reconverting the mass amount of data that represents the recorded digital images to a computer system where the user of the computer system can manipulate, transfer, or store the digital images. Thus, sophisticated encoding techniques have been developed to encode the ever increasing digital information into an ever smaller space in efforts to make digital cameras and digital camcorders more attractive for the users. Some of the digital image encoding techniques include JPEG, MPEG I and II. DVC or digital video (DV) is another encoding technique. Given the goal of digital image encoding is to encode as much data into as little of space as possible without losing detailed information, the DVC encoding technique produces variable length coding to produce more efficient coding. The variable length coding distributes coded data throughout a fixed encoded data structure. The hierarchy of the DVC coded building blocks is as follows: Video Frame (720xc3x97480 NTSC, 720xc3x97576 PAL)
DIF (Digital Interchange Format) Sequence (10 DIF Sequences per frame for NTSC, 12 for PAL)
Super Block (5 per DIF Sequence)
Video Segment (consists of 5 macro blocks or DIF blocks, 27 per DIF Sequence)
Macro or DIF Block (typically represents an 8xc3x9732 pixel area for NTSC, and a 16xc3x9716 pixel area for PAL)
Luminance and Chrominance Difference DCTs (4 luma (Y) and 2 chroma (Cr, Cb) per DIF block).
The variable length coding process for DVC is similar to other DCT based compression algorithms such as JPEG or MPEG. After quantization the AC coefficients are run length encoded which results in a series of run length-amplitude pairs. Run length refers to the number of consecutive zero AC coefficients, and amplitude refers to the amplitude of the AC coefficient at the end of the run of zero coefficients (e.g. run 3, amplitude 12 represents 3 zero amplitude coefficients followed by a coefficient amplitude equal to 12). The variable length code word associated with each run-amplitude pair is determined by a fixed Huffman table (Table 25, Helical-scan digital videocassette recording system using 6.35 mm magnetic tape for consumer use, IEC 61834-2 Part 2) page 169. For each DCT the dc coefficient, the variable length codewords, and an end of block (EOB) codeword are concatenated together to form the core of a variable length data stream.
Once the DCT data has been coded as an encoded data stream consisting of the dc coefficient, variable length codewords, and an EOB, the encoded data stream is stored into the fixed encoded data structure based on the hierarchy of the DVC encoded building blocks. The basic element of the fixed data structure is a DIF block that is shown in FIG. 9. The DIF block consists of a compressed macro block and three bytes, ID0-ID2. The three bytes ID0-ID2 identify the position of the compressed macro block in the data stream. Each compressed macro block includes data associated with 4 luminance (Y0-3) and 2 chroma difference (Cr, Cb) DCTs. Each DCT component starts with a 1.5 byte header consisting of a dc coefficient value, class number, and a DCT m0 bit. The DCT m0 bit indicates whether the DCT mode is the standard 8xc3x978 DCT or a dual 4xc3x978 (2-4xc3x978) DCT.
FIG. 9 is deceiving because it implies that all of the data associated with a particular DCT, such as Y0, is stored in the area marked Y0. The actual data distribution of the DCT components is significantly more complex. A three pass encoding of the DCT components distributes the variable length coded data associated with a particular DCT component. In some cases the variable length coded data associated with a particular DCT component can be distributed with other DCT components.
The first pass attempts to place the variable length coded data associated with a particular DCT in an area assigned to that DCT (e.g. luminance DCT Y0""s data would go into the DCT area labeled Y0). The luminance areas of the DIF block are allocated 12.5 bytes and the chrominance areas of the DIF block are allocated 8.5 bytes. The variable length coded data which is not stored in the allocated areas for the first pass is concatenated into individual DIF block overflow buffers (e.g. overflows from Y0 through Cb for DIF block 0 is stored in a DIF block 0 overflow buffer, Y0 through Cb for DIF block 1 is stored in a DIF block 1 overflow buffer, etc.).
For the second pass the data in the overflow buffers is distributed back into any free area in the associated DIF block (e.g. a Y0 overflow for DIF block 0 could go into any empty area left in Y1 through Cb in DIF block 0). Any coded data which cannot be placed back into the DIF block by this pass is concatenated into a single global overflow buffer, referred to as the video segment buffer (VSB).
For the third and final pass the coded data contained within the global buffer is distributed into any remaining unused area within the video segment.
FIG. 10 provides an example of the three pass encoding of the DCT components for the first two DIF blocks (macro blocks) of a video segment. The variable length coded AC coefficients for each DCT start as a variable length structure with an end of block (EOB) code concatenated to the end of the data. For DIF Block A, any code data exceeding 12.5 bytes for each of Y0, Y1, and Y2 and exceeding 8.5 bytes for Cr and Cb is placed into a buffer labeled DBA. For DIF Block B, the excess coded data for Y1 and Y2 is placed into a buffer labeled DBB. In pass 2 of the variable length coding, part of the coded data from DBA is placed back into DIF Block A. Because there is not enough space to contain all of the coded data, the excess coded data is stored into the video segment buffer (VSB). For DIF Block B, all of the coded data temporarily stored in DBB is absorbed back into the DIF block B, hence no additional data is added to the VSB buffer. During pass 3 the coded data left in VSB is placed into the open area that remains in DIF Block B.
To insure that the coded data fits in the allocated area during encoding, adjustment of the quantization levels for the AC coefficients controls the variable length coded data size. For example, as the quantization of the upper frequency AC coefficients gets more coarse (less granular) more of the AC coefficient values will drop to zero. Thus, the variable length coding process becomes more efficient as more AC coefficients drop to zero which results in a reduced storage requirement. However, some fine details for the original picture may be lost if too many AC coefficients values drop to zero.
The audio encoding for the DVC process is fairly straightforward providing for a 2""s complement representation of each audio sample for the 48 k, 44.1 k, and 32 k one channel modes (where, for example, 48 k represents a 48 kHz sampling rate and one channel means one stereo channel which is composed of a left and right source). There is also a 32 k two channel mode where each 16 bit audio sample undergoes a nonlinear compression down to 12 bits. The complete audio description is not included for the sake of brevity. Moreover, the present invention of a Variable Length Decode (VLD) engine skips over the non-video sections although system, audio, and video data is included in the input stream.
Once the audio and video have been coded, the variable length coded data is muxed with audio auxiliary, video auxiliary, and system data to form a data structure shown in FIG. 11. A set of 6 DIF blocks forms a single source packet used for isochronous transmission over firewire(trademark). Firewire(trademark) originally by Apple Computer, Inc. in 1995 and now standardized by the Institute of and Electronic Engineers as IEEE 1394-1995 is a high performance serial bus for digital/video interconnection. A set of 25 source packets is grouped into a single DIF sequence. The general structure of a DVC DIF sequence is defined in Part 2 of the Consumer audio/video equipment Digital interface, IEC 61883-2. The format shown in FIG. 11 is for NTSC; however, PAL is the same except that 12 DIF sequences (0.11) are used instead of the 10. Each DIF sequence contains the audio, video, and auxiliary data for 34,560 pixels of a video frame regardless of the video format (NTSC or PAL).
Given that the distribution of the variable length coded data associated with the DCT components can be inter-dispersed within a video segment such that the variable length coded AC coefficient areas can contain variable length coded data from other DCTs, decoding the inter-dispersed variable length coded data stored within the video segments presents a challenge and can demand considerable amounts of time and computing resources. Furthermore, conventional processing of the serial nature of the decode process requires that the variable length coded data be first shifted in and the length of the valid code determined before additional decoding can occur which severely limits decoding efficiency and the ability for parallel processing of the decode process. Therefore, it is desirable to provide an efficient apparatus and method of operating the same which decodes the variable length coded DVC data.
The present invention provides an apparatus for variable length decode (VLD) engines and methods for operating the same which result in improved performance of DVC decoder systems. The novel VLD engine is based on reconstructing overflow buffers associated with the variable length coded AC coefficient areas. Thus, according to one aspect of the invention, the VLD engine is operative to receive a video frame having a plurality of digital interchange format (DIF) sequences including a plurality of embedded AC coefficients and comprises a concatenation engine configured to contiguously format a plurality of DIF blocks of a DIF sequence to provide contiguous DCT blocks. A run-length amp pair generator is coupled to the concatenation engine configured to decode the contiguous DCT blocks to provide run-length amp pairs. The run-length amp pair includes a codeword having a run-length representing a number of consecutive zero AC coefficients and an amplitude representing a magnitude of a non-zero AC coefficient.
According to another aspect of the invention, a DIF sequence data storage is configured to store a plurality of DIF blocks having a plurality of DCT components. The concatenation engine includes a pass 1 engine coupled to the DIF sequence data storage to detect a DCT component and store remaining DCT components to a pass 2 overflow storage register of the DIF sequence data storage. A pass 2 engine is coupled to the pass 2 overflow storage register to detect complete DCT components from the remaining DCT components of the pass 2 overflow storage register and store incomplete DCT components to a pass 3 overflow storage register of the DIF sequence data storage. A pass 3 engine is coupled to the DIF sequence data storage, the pass 2 overflow storage register, and the pass 3 overflow storage register to contiguously format the plurality of DIF components from the DIF sequence data storage, the pass 2 overflow storage register, and the pass 3 overflow storage, respectively to provide the contiguous DCT blocks. The pass 1 engine, the pass 2 engine, and the pass 3 engine operate in parallel which provides even more efficient decoding of the variable length coded DVC data.
An apparatus and method for operating a VLD engine are provided whereby the VLD engine decodes variable length coded DVC data to provide codewords having run-length amp pairs. Improved decoding performance is achieved through reducing the number accesses to the DIF sequence data storage, maintaining data word boundaries for accesses to the DIF sequence data storage, and having separate working buffer areas for the pass engines.
Other aspects and advantages of the present invention can be seen upon review of the figures, the detailed description, and the claims which follow.